The present invention relates to a method and/or architecture for cyclic redundancy checking (CRC) generally and, more particularly, to a method and/or architecture for a FIFO with cyclic redundancy checking (CRC) in a programmable logic device (PLD).
The trend in networking applications is to rely more and more on specialized hardware logic to process network data frames for increased throughput. Traditional discrete logic and custom application specific integrated circuit (ASIC) approaches are steadily being displaced by new complex programmable logic devices (CPLDs). The CPLDs can offer flexible solutions and fast time to market.
A cyclic redundancy check (CRC) is used to detect transmission errors over communication channels in digital systems. When using the CRC technique, a modulo-2 sum (i.e., a CRC-sum) of bits of a message is calculated after grouping the message bits. The CRC-sum is appended to the transmitted message and used by the receiver to determine if the message was received correctly. The CRC-sum can be 8 or 16 bits, depending on the length of the message and the desired error-detection capability.
In one example, the CRC technique uses a polynomial expression to encode a message to be transmitted. An m-bit message M(x), where m is an integer, may be represented by a polynomial of order mxe2x88x921. A polynomial C(x) of order cxe2x88x921 can be used to encode the message M(x). An encoding expression R(x) can be calculated according to the equation R(x)=(xcM(x))/C(x). The transmitted message T(x) can be formed by the following equation T(x)=(xcM(x))⊕R(x). The transmitted message T(x) is exactly divisible by the encoding polynomial C(x). The receiver can determine if errors are present using the encoding polynomial. The receiver calculates (T(x)+E(x))/C(x), where E(x) represents any errors introduced during transmission. If the result is not zero, E(x) is non-zero and the received message is erroneous. If the result is zero, either no errors were introduced or E(x) is such that the CRC is not strong enough to detect the error. A suitable choice of the polynomial C(x) can ensure detection of errors.
Three methods of implementing CRC checking/generation for frame processing in networking applications are currently used. In a first method, CRC checking and generation logic is designed using the general purpose logic and routing resources available in a programmable logic device (PLD) with integrated FIFO blocks. However, the use of general purpose complex programmable logic device/field programmable gate array (CPLD/FPGA) cells and routing leads to (1) reduced performances due to the interconnect delays and (2) inefficient use of silicon real estate as the CRC components (divider, shifter, comparator, etc.) are implemented using general purpose look-up-table (LUT) or product term logic and interconnect resources.
A second method uses an ASIC with CRC checking and generation implemented via gate-array or standard cell logic. Using the ASIC approach leads to better performance than the first method. However, the nonrecurring engineering (NRE) costs and long turnaround time for ASICs can be detrimental to the fast time to market and short product lifetime that are typical in networking applications.
A third method using off the shelf FIFOs and CRC generator chips assembled onto a PC board can significantly improve performance. However, using off the shelf FIFOs and CRC generator chips assembled onto a PC board can be more expensive, uses precious board real estate, consumes more power, and is less reliable due to the large component count.
A CPLD having integrated FIFOs to buffer frame data and high-performance, integrated CRC checking and generating blocks at the input and output of the FIFOs would be desirable. Such a CPLD may ease the transition to processing data frames in hardware while providing a throughput similar to traditional ASIC solutions.
The present invention concerns a programmable logic device comprising one or more memory blocks that may be configured to check a CRC of an input and generate a CRC for an output.
The objects, features and advantages of the present invention include providing a method and/or architecture for implementing a FIFO with cyclic redundancy checking (CRC) in a programmable logic device (PLD) that may (i) provide PLD users with high performance custom building blocks to check and recompute data frame CRCs as they are switched, buffered and processed by user-specific logic designed using the PLD general purpose logic, (ii) provide logic for checking and generating data frame CRCs on the fly while maintaining a high throughput, (iii) provide application flexibility, (iv) guarantee performance of custom logic, (v) have low power consumption, (vi) require less silicon real estate than conventional CRC methods, and/or (vii) ease the transition to processing data frames in hardware while providing a throughput similar to traditional ASIC solutions.